EWDC-10 advance program and call for participation

[EWDC-10 organizer]

               Call for Participation and Advance Program


        10th EUROPEAN WORKSHOP ON DEPENDABLE COMPUTING (EWDC-10)
	========================================================
	    Vienna University of Technology, Vienna, Austria
	                     May 6-7, 1999


                 http://www.vmars.tuwien.ac.at/~ewdc10
		 -------------------------------------



Important Information:

            Last day for early registration: May 25th, 1999

	    Detailed information about the workshop (CFP, registration
	    information and forms, hotel information, etc.) is available on
	    the workshop Web page <http://www.vmars.tuwien.ac.at/~ewdc10>.

	    The number of hotel rooms that has been pre-reserved for
	    workshop participants is limited. Please book your hotel room as
	    soon as possible as the hotels will keep the pre-reservation only
	    until April 10th.





                          WORKSHOP PROGRAMME
			  ==================


THURSDAY, MAY 6, 1999

 8:00- ...  Registration

 8:15- 8:30 Opening

 8:30-10:00 Session 1: Automatic Verification and Validation

            Extending and Automating Classical Safety Analyses to
	    Rationalise and Simplify Complex Safety Assessments
	    (Yannis Papadopoulos, John McDermid)

	    Guiding the Experimental Validation of Dependable Commercial
	    Control and Supervision Systems by a Formal Approach
	    (Alberto Arazo, Yves Crouzet)

	    Towards an Automatic Verification of Timed Automata Networks
	    (Conrado Daws, Hassen Saidi)

10:00-10:30 Coffee Break

10:30-11:30 Session 2: Invited Talk

            further details to be announced

11:30-12:30 Session 3: Fault-Tolerance Architectures

            Design of a Vital Platform for Railway Signalling Applications
	    (Heinz Kantz, Alfred Veider)

	    Control Flow Monitoring for a Time-Triggered Communication
	    Controller
	    (Thomas Galla, Michael Sprachmann, Andreas Steininger,
	    Christopher Temple)

12:30-14:00 Lunch

14:00-16:00 Session 4: Tools for Testing and Testability Analysis

            An Efficient Technique of Testbench Generation for VHDL Models
	    (Stanislaw Deniziak, Krzysztof Sapiecha)

	    A Test Ordering Tool for Object-Oriented Programs
	    (Y. Labiche, Pascale Thevenod-Fosse, Helene Waeselynck)

	    An Efficient On-line-Test and Recover Scheme for Embedded
	    Processors
	    (M. Pflanz, H.T. Vierhaus)

	    Testability Analysis in High-Level Synthesis
	    (Peter Bukovjan, Meryem Marzouki, Walid Maroufi)

16:00-16:30 Coffee Break

16:30-18:00 Session 5: Short Presentations

	    Self-Evolving Dependable Real-Time Systems
	    (Gerhard Fohler, Sasi Punnekkat)

	    A New Method of Testing Complex Circuits Implemented using
	    In-System Programmable Devices
	    (Jacek Binda)

            High-level Petri Net Modelling of Phased Mission Systems
	    (Andrea Bondavalli, Ivan Mura)

	    Limitations of Classical Fault Models
	    (M. Renovell, F. Azais, Y. Bertrand)

	    Telecommunications Systems Design Complexity and Risk Assessment
	    based on System Metrics
	    (Ognjen Prnjat, Lionel Sacks)

	    Heuristic Worst-Case Execution Time Analysis
	    (Pavel Atanassov, Stefan Haberl, Peter Puschner)

	    Causality Checking Procedures for Distributed Environment
	    (Henryk Krawczyk, Jerzy Proficz)

20:00       Workshop Dinner



FRIDAY, MAY 7, 1999


 8:30-10:00 Session 6: Synthesis and Diagnosis of Hardware

            Detection of Delay Faults in Large In-System Reprogrammable FPGAs
	    (Andrzej Krasniewsky)

	    Enhanced Diagnostics of MIMD Systems
	    (A. Derezinska, Janusz Sosnowski)

	    Behavioural VHDL Description Based Synthesis of Self-Checking
	    Circuits
	    (Andras Petri jr., Andras Pataricza, Endre Selenyi)

10:00-10:30 Coffee Break

10:30-12:30 Session 7: Modelling and Simulation of Dependable Systems

            Transformation of Guarded Statecharts for Quantitative
	    Evaluation of Dependable Embedded Systems
	    (Mario Dal Cin, G. Huszerl, K. Kosmidis)

	    A Simulation Approach to Evaluate and Assess Dependability
	    Properties of Integrated Mechatronic Systems
	    (Karl E. Grosspietsch, B. Straube, W. Vermeiren)

	    Behavioral Analysis in the Presence of Faults of Dependable
	    Systems Modeled with RDD-100
	    (Yannick Le Guedard, Mohamed Kaaniche, Jean Arlat, Thierry Boyer)

	    A Simulation Tool for Dependability-Oriented Design of
	    Multimedia Applications
	    (L. Romano, A. Coronato, A. Mazzeo, N. Mazzocca)

12:30-14:00 Lunch

14:00-15:30 Session 8: Error Detection and Handling

            Automatic Generation of Diversified Program Variants Optimized
	    to Detect Hardware Faults
	    (Markus Jochim)

	    On N-Version Programming and Exception Handling
	    (Alexander Romanovsky)

	    Concurrent Error Detection of Program Execution Based on
	    Statechart Specification
	    (Istvan Majzik, Judit Javorszky, Andras Pataricza, Endre Selenyi)

15:30-16:00 Coffee Break

15:00-17:30 Session 9: Fault Injection and Self Test

            The Effects of Workload Input Domain on Fault Injection Results
	    (Peter Folkesson, Johan Karlsson)

	    Fault Tolerant Control System Evaluation by Fault Injection
	    Method
	    (Zeljko Hocenski, Goran Martinovic)

	    Multi-Input Shift Register with Zero Output and Two-Output Space
	    Compactor for BIST
	    (Krzysztof Gucwa, Andrzej Hlawiczka)

17:30       Concluding Remarks and Wrap-Up

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