[Acpc-l] Vortrag: Prof. Thomas Sterling, 20. 6. 2000
Maria Cherry
Maria Cherry <maria@par.univie.ac.at>
Mon, 19 Jun 2000 13:57:37 +0200 (MET DST)
UNIVERSITAET WIEN INSTITUT FUER SOFTWAREWISSENSCHAFT
gemeinsam mit
FWF-Projekt Spezialforschungsbereich F011 "AURORA"
EINLADUNG ZU EINEM VORTRAG IM RAHMEN DES AURORA-KOLLOQUIUMS
The MIND Chip Architecture: Towards the Next Generation
of Processor-in-Memory Devices
Prof. Thomas Sterling
Center for Advanced Computing Research,
California Institute of Technology and High
Performance Computing Group,
NASA Jet Propulsion Laboratory
ZEIT: Dienstag, 20. 6. 2000, 16.00 Uhr s.t.
ORT: Institut fuer Softwarewissenschaft
1090 Wien, Liechtensteinstrasse 22,
Seminarraum, Mezzanin
Abstract
The steady increase in integrated circuit device density, reflected if not
driven by the
so-called Moore's Law, is making innovative classes of computer architecture
practical,
which were infeasible only a short time ago. Of equal importance, conventional
processor
architecture techniques are incapable of optimally exploiting the availability
of logic
gates per chip, also suggesting the need for alternate structures. Examination
of
effective computation per transistor over the recent microprocessor history
demonstrates
declining efficiency even as overall performance increases. Other trends as
well
motivate new structures for exploiting the wealth of chip level resources.
While device
density is increasing at a significant rate, microprocessor clock rate is
increasing much
more slowly. Even so, memory access rate is improving much more slowly than
that. The
implication is that the "memory wall", the gap between the data requirements of
high
speed microprocessors, and the ability of memory chips to supply them, is
worsening.
Ironically, DRAM memory density is increasing more rapidly than CMOS logic
density,
requiring a diminishing number of memory modules per processor chip. Finally,
recent
advances in fabrication methodology has made practical the co-integration of
both CMOS
logic and DRAM memory cells on the same semiconductor die. Recognition of these
trends
is motivating new classes of computer architecture that combine multiple system
units on
a single die. System on a Chip (SOC), SMP on a chip (SMPoC), and Processor in
Memory
(PIM) including IRAM are all examples of this revolution in computer
architecture. But
of these, only PIM exploits the important property of DRAM that exposes enormous
memory
bandwidth on-chip compared to that available off chip; on the order of 100
Terabits per
second per chip for certain organizations. In its most initial form, PIM places
simple
ALUs across the memory stack row buffer making possible several Gops of
performance per
PIM chip without the need for temporal locality and at order of magnitude
reduced power
consumption than conventional systems. Yet practical operational considerations
limit
the usefulness of such basic PIM structures and their entry in the commercial
market has
been slow.
The Gilgamesh (Billion Logic Gate Assemblies - Mesh) project is developing the
MIND
(Memory, Intelligent, Network Devices) chip, an advanced scalable processor in
memory
architecture for spaceborne and general robotic embedded applications. It
overcomes the
logical and efficiency limitations of earlier PIM devices by incorporating
several
critical mechanisms not previously found in PIM. Message driven computation
employing
light weight Parcels permits direct memory chip to memory chip interaction. A
new
scalable address mapping scheme permits the direct manipulation of virtually
addressed
objects in a distributed system. A multithreaded task switching and management
capability provides overlapping use of parallel on-chip resources for high
efficiency of
memory and I/O channels. A distributed object-based computing model called
"macroservers" provides a logical framework for organization multiple MIND
processor/memory nodes to perform a single parallel task for high performance
and large
data sets. This seminar will present the technology opportunities and
architecture
challenges defining the design tradeoff space of advanced PIM devices. The
architecture
approach and some detailed mechanisms will be described demonstrating the
concept of the
MIND architecture. The talk will conclude with a brief discussion of future
work and
immediate plans.
***************************
Im Anschluss an diesen Vortrag (ca. 17.00 ct) wird Prof. Zima im
Forschungsprivatissimum einen Vortrag ueber "Macroservers" halten.